M62364FP/GP

REJ03D0875-0400 Rev.4.00 Oct 02, 2009

Page 2 of 8

Pin Arrangement

GND

RESET

Do

LD

CLK

DI

23

22

21

20

19

18

17

16

9

15

10

14

11

13

12

8

7

6

5

4

3

2

1

M62364FP/GP

(Top view)

Outline: PRSP0024GA-A (24P2Q-A)

PLSP0024JA-A (24P2E-A)

Pin Description

Pin No.

Pin Name

Function

8

DI

Serial data input

17

Serial data output

7

CLK

Shift clock input. Input data of DI are taken into the 12-bit shift register on a rising edge of

the clock.

6

LD

A low state enables data loading to the 12-bit shift register.

During a rising edge of LD, the data will be loaded to the output register.

19

RESET

Reset 8-bit latches

2

3

10

11

14

15

22

23

D/A converter output with 8-bit resolution

5

Power supply

20

GND

Ground

1

4

9

12

13

16

21

24

D/A converter input

18

D/A converter reference voltage input