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ATmega169P Datasheet(PDF) 333 Page - ATMEL Corporation |
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ATmega169P Datasheet(HTML) 333 Page - ATMEL Corporation |
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333 / 393 page ![]() 333 8018N–AVR–08/09 ATmega169P Note: 1. In SPI Programming mode the minimum SCK high/low period is: - 2 t CLCL for fCK < 12 MHz - 3 t CLCL for fCK > 12 MHz Figure 28-4. SPI Interface Timing Requirements (Master Mode) Figure 28-5. SPI Interface Timing Requirements (Slave Mode) MOSI (Data Output) SCK (CPOL = 1) MISO (Data Input) SCK (CPOL = 0) SS MSB LSB LSB MSB ... ... 61 22 3 45 8 7 MISO (Data Output) SCK (CPOL = 1) MOSI (Data Input) SCK (CPOL = 0) SS MSB LSB LSB MSB ... ... 10 11 11 12 13 14 17 15 9 X 16 |
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