ATMEGA64A datasheet(21/392 Pages) ATMEL

21 / 392 page

8160C–AVR–07/09

ATmega64A

Figure 7-3.

On-chip Data SRAM Access Cycles

7.3

EEPROM Data Memory

The ATmega64A contains 2K bytes of data EEPROM memory. It is organized as a separate

data space, in which single bytes can be read and written. The EEPROM has an endurance of at

least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described

in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and

the EEPROM Control Register.

“Memory Programming” on page 295 contains a detailed description on EEPROM programming

in SPI, JTAG, or Parallel Programming mode.

7.3.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 7-5 on page 34. A self-timing function,

however, lets the user software detect when the next byte can be written. If the user code con-

tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered

power supplies, V

CC is likely to rise or fall slowly on Power-up/down. This causes the device for

some period of time to run at a voltage lower than specified as minimum for the clock frequency

used. See “Preventing EEPROM Corruption” on page 22. for details on how to avoid problems in

these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

7.3.2

EEPROM Write During Power-down Sleep Mode

When entering Power-down Sleep mode while an EEPROM write operation is active, the

EEPROM write operation will continue, and will complete before the Write Access time has

passed. However, when the write operation is completed, the oscillator continues running, and

clk

Data

Address

Address Valid

Compute Address

CPU

Memory Access Instruction

Next Instruction

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