ATmega328P datasheet(84/448 Pages) ATMEL

84 / 448 page

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

(one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer

function.

PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source.

• ICP1/CLKO/PCINT0 – Port B, Bit 0

ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.

CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin. The

divided system clock will be output if the CKOUT Fuse is programmed, regardless of the

PORTB0 and DDB0 settings. It will also be output during reset.

PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source.

Table 13-4 and Table 13-5 on page 85 relate the alternate functions of Port B to the overriding

signals shown in Figure 13-5 on page 80. SPI MSTR INPUT and SPI SLAVE OUTPUT consti-

tute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

Notes:

1. INTRC means that one of the internal RC Oscillators are selected (by the CKSEL fuses),

EXTCK means that external clock is selected (by the CKSEL fuses)

Table 13-4.

Overriding Signals for Alternate Functions in PB7..PB4

Signal

Name

PB7/XTAL2/

TOSC2/PCINT7(1)

PB6/XTAL1/

TOSC1/PCINT6(1)

PB5/SCK/

PCINT5

PB4/MISO/

PCINT4

PUOE

INTRC • EXTCK+

AS2

INTRC + AS2

SPE • MSTR

PUOV

PORTB5 • PUD

PORTB4 • PUD

DDOE

INTRC • EXTCK+

AS2

INTRC + AS2

SPE • MSTR

DDOV

0000

PVOE

SPE • MSTR

PVOV

SCK OUTPUT

SPI SLAVE

OUTPUT

DIEOE

INTRC • EXTCK +

AS2 + PCINT7 •

PCIE0

INTRC + AS2 +

PCINT6 • PCIE0

PCINT5 • PCIE0

PCINT4 • PCIE0

DIEOV

(INTRC + EXTCK) •

AS2

INTRC • AS2

PCINT7 INPUT

PCINT6 INPUT

PCINT5 INPUT

SCK INPUT

PCINT4 INPUT

SPI MSTR INPUT

AIO

Oscillator Output

Oscillator/Clock

Input

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ATmega328P Datasheet(PDF) 84 Page - ATMEL Corporation

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