73 / 99 page
PRELIMINARY
PSoC®3: CY8C36 Family Data Sheet
Document Number: 001-53413 Rev. *B
Page 73 of 99
11.5.7 VDAC
INL
Integral non linearity
RL 600
Ω, CL=15 pF
-
-
±
1LSB
DNL
Differential non linearity
RL 600
Ω, CL=15 pF
-
-
±
0.5
LSB
Ezs
Zero scale error
-
0
±
1LSB
Eg
Gain error
Uncompensated
-
-
2.5
%
Temperature compensated
-
-
TBD
%
IDAC_ICC
DAC current low speed mode[10]
Code = 0
-
-
100
µA
IDAC_ICC
DAC current high speed mode[10]
Code = 0
-
-
500
µA
Table 11-26. IDAC (Current Digital-to-Analog Converter) AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Fdac
Update rate
-
-
8
Msps
Tsettle
Settling time to 0.5LSB
Full scale transition, 600
Ω load,
CL = 15 pF
Fast mode
Independent of IDAC range setting
(Iout)
-
-
100
ns
Slow mode
Independent of IDAC range setting
(Iout)
-
-
1000
ns
Table 11-25. IDAC (Current Digital-to-Analog Converter) DC Specifications
(continued)
Parameter
Description
Conditions
Min
Typ
Max
Units
Table 11-27. VDAC (Voltage Digital-to-Analog Converter) DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Rout
Output resistance[10]
High
Vout = 4V
-
16
-
k
Ω
Low
Vout = 1V
-
4
-
k
Ω
Vout
Output voltage range[10]
High
Code = 255, Vdda > 5V
-
4
-
V
Low
Code = 255
-
1
-
V
INL
Integral non linearity
CL=15 pF
-
-
±
1.6
LSB
DNL
Differential non linearity
CL=15 pF
-
-
±
1LSB
Ezs
Zero scale error
-
-
±
1LSB
Eg
Gain error
Uncompensated
-
-
3
%
Temperature compensated
-
-
TBD
%
VDAC_ICC
DAC current low speed mode[10]
Code = 0
-
-
100
µA
VDAC_ICC
DAC current high speed mode[10]
Code = 0
-
-
500
µA
Table 11-28. VDAC (Voltage Digital-to-Analog Converter) AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Fdac
Update rate[10]
1V mode
-
-
1
Msps
Update rate[10]
4V mode
-
-
250
Ksps
Tsettle
Settling time to 0.5LSB[10]
Full scale transition, CL = 15 pF
High[10]
Vout = 4V
-
-
4000
ns
Low[10]
Vout = 1V
-
-
1000
ns
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