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PRELIMINARY
PSoC®5: CY8C52 Family Data Sheet
Document Number: 001-55034 Rev. *A
Page 73 of 85
Figure 11-4. Synchronous Write Cycle Timing
Table 11-46. Synchronous Write Cycle Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
T
EMIF Clock period
30.3
-
-
ns
Tcp
EM_Clock Period
30.3
-
ns
Tceld
EM_Clock low to EM_CEn low
-
5
ns
Tcehd
EM_Clock high to EM_CEn high
T/2 - 2
-
ns
Taddrv
EM_Clock low to EM_Addr valid
-
5
ns
Taddriv
EM_Clock high to EM_Addr invalid
T/2 - 2
-
ns
Tweld
EM_Clock low to EM_WEn low
-
5
ns
Twehd
EM_Clock high to EM_WEn high
T/2 - 2
-
ns
Tds
Data valid after EM_Clock low
-
5
ns
Tadscld
EM_clock low to EM_ADSCn low
-
5
ns
Tadschd
EM_clock high to EM_ADSCn high
T/2 - 2
-
ns
Address
Tcp
Tceld
Taddrv
Tcehd
Taddriv
Twehd
Tweld
Tds
Data
Tadscld
Tadschd
EM_ Clock
EM_ CEn
EM_ Addr
EM_ WEn
EM_ Data
EM_ ADSCn
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