ST7548T datasheet(21/50 Pages) SITRONIX

21 / 50 page

ST7548T

Ver 1.2

21/50

2006/03/16

DISPLAY DATA RAM (DDRAM)

The ST7548T contains a 66X102 bit static RAM that stores the display data. The display data RAM store the dot data for

the LCD. It has a 66(8 pageX8 bit +1 pageX1 bit +1 pageX1 bit) X 102 . There is a direct correspondence between

X-address and column output number. It is 66-row by 102-column addressable array. Each pixel can be selected when the

page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines (0~63 COM) and 8th page with

single line (D0) (64COM) and 9th page with a single line (D0) (COMS for ICON). Data is read from or written to the 8 lines

of each page directly through D0 to D7. The display data of D0 to D7 from the microprocessor correspond to the LCD

common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller

operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD

flicker.

Page Address Circuit

This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by

only the “Set Page” instruction. Page Address 9 is a special RAM area for the icons and display data D0 is only valid.

Line Address Circuit

This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line

Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of

on-chip RAM as shown in figure 10. It incorporates 7-bit Line Address register changed by only the initial display line

instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line

counter which is increased by CL signal and generates the line address for transferring the 102-bit RAM data to the display

data latch circuit. When icon is selected by setting icon page address, display data of icons are not scrolled because the

MPU cannot access Line Address of icons.

Column Address Circuit

Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM. The display

data RAM column address is specified by the Column Address Set command. The specified column address is

incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed

continuously.

segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing MX select instruction.

SEG Output

SEG0

SEG101

“0”

seg0

Segment Address à seg101

“1”

seg101 ß Segment Address ß seg0

ADDRESSING

Data is downloaded in bytes into the RAM matrix of ST7548T. The display RAM has a matrix of 66 by 102 bits. The

address pointer addresses the columns. The address ranges are: X 0 to 101 (1100101),Y 0 to 9 (1001) .Addresses outside

these ranges are not allowed.In vertical addressing mode (V=1) the Y address increments after each byte. After the last Y

address (Y = 8), Y wraps around to 0 and X increments to address the next column.In horizontal addressing mode (V=0)

the X address increments after each byte. After the last X address(X = 101) X wraps around to 0 and Y increments to

address the next row.After the very last address (X = 101, Y = 8) the address pointers wrap around to address (X = 0, Y =0)

ST7548T Datasheet(PDF) 21 Page - Sitronix Technology Co., Ltd.

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