ST7549T datasheet(45/52 Pages) SITRONIX

45 / 52 page

ST7549T

Ver 1.3

45/52

2005/12/06

(VDD=1.8V,Ta=-30~85

℃)

Rating

Item

Signal

Symbol

Condition

Min.

Max.

Units

Serial Clock Period

tSCYC

500

—

SCL “H” pulse width

tSHW

250

—

SCL “L” pulse width

SCL

tSLW

250

—

Data setup time

tSDS

—

Data hold time

tSDH

—

CS-SCL time

tCSS

—

CS-SCL time

CSB

tCSH

350

—

*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.

*2 All timing is specified using 20% and 80% of VDD as the standard.

SERIAL INTERFACE(I

2C Interface)

S DA

S CL

tBUF

tDH;STA

tLOW

tHD;DAT

tHIGH

tSU;DAT

(VDD=3.3V,Ta=-30~85

℃)

Rating

Item

Signal Symbol

Condition

Min.

Max.

Units

SCL clock frequency

SCL

FSCLK

400

kHZ

SCL clock low period

SCL

TLOW

1.3

SCL clock high period

SCL

THIGH

0.6

Data set-up time

TSU;Data

100

Data hold time

THD;Data

0.9

SCL,SDA rise time

SCL

20+0.1Cb 300

SCL,SDA fall time

SCL

20+0.1Cb 300

Capacitive load represented by each bus line

400

Setup time for a repeated START condition

TSU;SUA

0.6

Start condition hold time

THD;STA

0.6

Setup time for STOP condition

TSU;STO

0.6

Tolerable spike width on bus

TSW

BUS free time between a STOP and START condition SCL

TBUF

1.3

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