TDA8029C2 datasheet(39/59 Pages) NXP

39 / 59 page

9397 750 14145

Product data sheet

Rev. 03 — 22 February 2005

39 of 59

Philips Semiconductors

TDA8029

Low power single card reader

8.10.3.6

Power control register (PCR)

This register is used for starting or stopping card sessions.

Table 67:

CCR - Clock conﬁguration register (address 1h) bit allocation

Bit

Symbol

SHL

CST

AC2

AC1

AC0

Reset

000000

Access

read and write

Table 68:

CCR - Clock conﬁguration register (address 1h) bit description

Bit

Symbol

Description

7 and 6

Not used.

SHL

Select HIGH Level. This bit determines how the clock is stopped when bit CST = 1. If

SHL = 0, then the clock is stopped at LOW level, if SHL = 1 at HIGH level.

CST

Clock Stop. In case of an asynchronous card, bit CST deﬁnes whether the clock to the

card is stopped or not. If CST = 1, then the clock is stopped. If CST = 0, then the clock is

determined by bits AC[2:0] according to Table 69. All frequency changes are

synchronous, ensuring that no spike or unwanted pulse width occurs during changes.

Synchronous Clock. In the event of a synchronous card, then pin CLK is the copy of the

value of bit SC. In reception mode, the data from the card is available to bit UR0 after a

read operation of register URR. In transmission mode, the data is written on the I/O line

of the card when register UTR has been written to.

2 to 0

AC[2:0]

Asynchronous card clock. When CST = 0, the clock is determined by the state of these

bits according to Table 69.

fint is the frequency delivered by the internal oscillator clock circuitry.

For switching from 1

⁄nfXTAL to 1⁄2fint and reverse, only the bit AC2 must be changed (AC1

and AC0 must remain the same). For switching from 1

⁄nfXTAL or 1⁄2fint to stopped clock and

reverse, only bits CST and SHL must be changed.

When switching from 1

⁄nfXTAL to 1⁄2fint and reverse, a delay can occur between the

command and the effective frequency change on pin CLK. The fastest switch is from

⁄2fXTAL to 1⁄2fint and reverse, the best regarding duty cycle is from 1⁄8fXTAL to 1⁄2fint and

reverse. The bit CLKSW in register MSR tells the effective switch moment.

In case of fCLK =fXTAL, the duty cycle must be ensured by the incoming clock signal on

pin XTAL1.

Table 69:

CLK value for an asynchronous card

AC2

AC1

AC0

CLK

000

fXTAL

001

⁄2fXTAL

010

⁄4fXTAL

011

⁄8fXTAL

100

⁄2fint

101

⁄2fint

110

⁄2fint

111

⁄2fint

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