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dsPIC33FJ32GS608 Datasheet(PDF) 238 Page - Microchip Technology |
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dsPIC33FJ32GS608 Datasheet(HTML) 238 Page - Microchip Technology |
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238 / 416 page ![]() dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 DS70591B-page 238 Preliminary 2009 Microchip Technology Inc. bit 7-6 DTC<1:0>: Dead Time Control bits 11 = Dead Time Compensation mode 10 = Dead time function is disabled 01 = Negative dead time actively applied for Complementary Output mode 00 = Positive dead time actively applied for all output modes bit 5 DTCP: Dead Time Compensation Polarity bit(4) 1 = If DTCMPx = 0, PWMxL is shortened, and PWMxH is lengthened If DTCMPx = 1, PWMxH is shortened, and PWMxL is lengthened 0 = If DTCMPx = 0, PWMxH is shortened, and PWMLx is lengthened If DTCMPx = 1, PWMxL is shortened, and PWMxH is lengthened bit 4 Unimplemented: Read as ‘0’ bit 3 MTBS: Master Time Base Select bit 1 = PWM generator uses the secondary master time base for synchronization and the clock source for the PWM generation logic (if secondary time base is available) 0 = PWM generator uses the primary master time base for synchronization and the clock source for the PWM generation logic bit 2 CAM: Center-Aligned Mode Enable bit(2,3) 1 = Center-Aligned mode is enabled 0 = Edge-Aligned mode is enabled bit 1 XPRES: External PWM Reset Control bit(5) 1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base mode 0 = External pins do not affect PWM time base bit 0 IUE: Immediate Update Enable bit 1 = Updates to the active MDC/PDCx/SDCx registers are immediate 0 = Updates to the active PDCx registers are synchronized to the PWM time base REGISTER 16-11: PWMCONx: PWM CONTROL REGISTER (CONTINUED) Note 1: Software must clear the interrupt status here, and in the corresponding IFS bit in the Interrupt Controller. 2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 3: These bits should not be changed after the PWM is enabled (PTEN = 1). 4: For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored. 5: To operate in External Period Reset mode, configure FCLCONx<CLMOD> = 0 and PWMCONx<ITB> = 1. |
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