DSPIC33FJ32GS608 datasheet(36/416 Pages) MICROCHIP

36 / 416 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591B-page 36

Preliminary

 2009 Microchip Technology Inc.

3.3

Special MCU Features

The

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 features a 17-bit by

17-bit single-cycle multiplier that is shared by both the

MCU ALU and DSP engine. The multiplier can perform

signed, unsigned and mixed sign multiplication. Using a

17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication

not only allows you to perform mixed sign multiplication,

it also achieves accurate results for special operations,

such as (-1.0) x (-1.0).

The

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 supports 16/16 and

32/16 divide operations, both fractional and integer. All

divide instructions are iterative operations. They must be

executed within a REPEAT loop, resulting in a total

execution time of 19 instruction cycles. The divide

operation can be interrupted during any of those

19 cycles without loss of data.

A 40-bit barrel shifter is used to perform up to a 16-bit

left or right shift in a single cycle. The barrel shifter can

be used by both MCU and DSP instructions.

FIGURE 3-1:

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 CPU

CORE BLOCK DIAGRAM

Instruction

Decode &

Control

PCH

PCL

Program Counter

16-Bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

Stack

Control

Logic

Loop

Control

Logic

Data Latch

Address

Latch

Control Signals

to Various Blocks

To Peripheral Modules

Data Latch

Address

Latch

X RAM

Y RAM

Address Generator Units

Y Data Bus

X Data Bus

DSP Engine

Divide Support

PSV & Table

Data Access

Control Block

Program Memory

Data Latch

Address Latch

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