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dsPIC33FJ32GS608 Datasheet(PDF) 245 Page - Microchip Technology |
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dsPIC33FJ32GS608 Datasheet(HTML) 245 Page - Microchip Technology |
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245 / 416 page  2009 Microchip Technology Inc. Preliminary DS70591B-page 245 dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 bit 3-2 CLDAT<1:0>: State(2) for PWMxH and PWMxL Pins if CLMOD is Enabled bits FCLCONx<IFLTMOD> = 0: Normal Fault mode If current-limit active, then CLDAT<1> provides state for PWMxH If current-limit active, then CLDAT<0> provides state for PWMxL FCLCONx<IFLTMOD> = 1: Independent Fault mode CLDAT<1:0> is ignored bit 1 SWAP: SWAP PWMxH and PWMxL pins bit 1 = PWMxH output signal is connected to PWMxL pins; PWMxL output signal is connected to PWMxH pins 0 = PWMxH and PWMxL pins are mapped to their respective pins bit 0 OSYNC: Output Override Synchronization bit 1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base 0 = Output overrides via the OVDDAT<1:0> bits occur on next CPU clock boundary REGISTER 16-19: IOCONx: PWM I/O CONTROL REGISTER (CONTINUED) Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1). 2: State represents the active/inactive state of the PWM depending on the POLH and POLL bit settings. |
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