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dsPIC33FJ32GS608 Datasheet(PDF) 285 Page - Microchip Technology |
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dsPIC33FJ32GS608 Datasheet(HTML) 285 Page - Microchip Technology |
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285 / 416 page  2009 Microchip Technology Inc. Preliminary DS70591B-page 285 dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-4: CiFCTRL: ECAN™ FIFO CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 DMABS<2:0> — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FSA<4:0> bit 7 bit 0 Legend: C = Writeable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in DMA RAM 101 = 24 buffers in DMA RAM 100 = 16 buffers in DMA RAM 011 = 12 buffers in DMA RAM 010 = 8 buffers in DMA RAM 001 = 6 buffers in DMA RAM 000 = 4 buffers in DMA RAM bit 12-5 Unimplemented: Read as ‘0’ bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = Read buffer RB31 11110 = Read buffer RB30 • • • 00001 = Tx/Rx buffer TRB1 00000 = Tx/Rx buffer TRB0 |
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