DSPIC33FJ32GS608 datasheet(117/416 Pages) MICROCHIP

117 / 416 page

 2009 Microchip Technology Inc.

Preliminary

DS70591B-page 117

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

6.1

System Reset

The

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 families of devices

have two types of Reset:

• Cold Reset

•Warm Reset

A cold Reset is the result of a Power-on Reset (POR)

or a Brown-out Reset (BOR). On a cold Reset, the

FNOSC Configuration bits in the FOSC Configuration

A warm Reset is the result of all the other Reset

sources, including the RESET instruction. On warm

Reset, the device will continue to operate from the

current clock source as indicated by the Current

Oscillator Selection (COSC<2:0>) bits in the Oscillator

Control (OSCCON<14:12>) register.

The device is kept in a Reset state until the system

power supplies have stabilized at appropriate levels

and the oscillator clock is ready. The sequence in

which this occurs is detailed below and is shown in

Figure 6-2.

POR Reset: A POR circuit holds the device in

Reset when the power supply is turned on. The

POR circuit is active until VDD crosses the VPOR

threshold and the delay, TPOR, has elapsed.

BOR Reset: The on-chip voltage regulator has

a BOR circuit that keeps the device in Reset

until VDD crosses the VBOR threshold and the

delay, TBOR, has elapsed. The delay, TBOR,

ensures that the voltage regulator output

becomes stable.

PWRT Timer: The programmable power-up

timer continues to hold the processor in Reset

for a specific period of time (TPWRT) after a

BOR. The delay TPWRT ensures that the system

power

supplies

have

stabilized

the

appropriate level for full-speed operation. After

the delay, TPWRT, has elapsed, the SYSRST

becomes inactive, which in turn enables the

selected oscillator to start generating clock

cycles.

Oscillator Delay: The total delay for the clock to

be ready for various clock source selections is

given in Table 6-1. Refer to Section 9.0

“Oscillator Configuration” for more information.

When the oscillator clock is ready, the processor

begins execution from location 0x000000. The

user application programs a GOTO instruction at

the Reset address, which redirects program

execution to the appropriate start-up routine.

The Fail-Safe Clock Monitor (FSCM), if enabled,

begins to monitor the system clock when the

system clock is ready and the delay, TFSCM,

elapsed.

TABLE 6-1:

OSCILLATOR DELAY

Oscillator Mode

Oscillator

Start-up Delay

Oscillator

Start-up Timer

PLL Lock Time

Total Delay

FRC, FRCDIV16, FRCDIVN

TOSCD(1)

——

TOSCD(1)

FRCPLL

TOSCD(1)

—TLOCK(3)

TOSCD + TLOCK(1,3)

TOSCD(1)

TOST(2)

—TOSCD + TOST(1,2)

TOSCD(1)

TOST(2)

—TOSCD + TOST(1,2)

————

XTPLL

TOSCD(1)

TOST(2)

TLOCK(3)

TOSCD + TOST +

TLOCK(1,2,3)

HSPLL

TOSCD(1)

TOST(2)

TLOCK(3)

TOSCD + TOST +

TLOCK(1,2,3)

ECPLL

—

TLOCK(3)

LPRC

TOSCD(1)

——

TOSCD(1)

Note 1:

TOSCD = Oscillator start-up delay (1.1

s max for FRC, 70 s max for LPRC). Crystal oscillator start-up

times vary with crystal characteristics, load capacitance, etc.

TOST = Oscillator start-up timer delay (1024 oscillator clock period). For example, TOST = 102.4

s for a

10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.

TLOCK = PLL lock time (1.5 ms nominal) if PLL is enabled.

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