DSPIC33FJ32GS608 datasheet(178/416 Pages) MICROCHIP

178 / 416 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591B-page 178

Preliminary

 2009 Microchip Technology Inc.

The DMA controller features four identical data transfer

channels. Each channel has its own set of control and

STATUS registers. Each DMA channel can be

configured to copy data either from buffers stored in

dual port DMA RAM to peripheral SFRs or from

peripheral SFRs to buffers in DMA RAM.

The DMA controller supports the following features:

• Word or byte sized data transfers.

• Transfers from peripheral to DMA RAM or DMA

RAM to peripheral.

• Indirect Addressing of DMA RAM locations with or

without automatic post-increment.

• Peripheral Indirect Addressing – In some

peripherals, the DMA RAM read/write addresses

may be partially derived from the peripheral.

• One-Shot Block Transfers – Terminating DMA

transfer after one block transfer.

• Continuous Block Transfers – Reloading DMA

RAM buffer start address after every block

transfer is complete.

• Ping-Pong Mode – Switching between two DMA

RAM start addresses between successive block

transfers, thereby filling two buffers alternately.

• Automatic or manual initiation of block transfers.

For each DMA channel, a DMA interrupt request is

generated when a block transfer is complete.

Alternatively, an interrupt can be generated when half of

the block has been filled.

8.1

DMAC Registers

Each DMAC Channel x (x = 0, 1, 2, or 3) contains the

following registers:

• A 16-bit DMA Channel Control register

(DMAxCON)

• A 16-bit DMA Channel IRQ Select register

(DMAxREQ)

• A 16-bit DMA RAM Primary Start Address Offset

• A 16-bit DMA RAM Secondary Start Address

Offset register (DMAxSTB)

• A 16-bit DMA Peripheral Address register

(DMAxPAD)

• A 10-bit DMA Transfer Count register (DMAxCNT)

An additional pair of STATUS registers, DMACS0 and

DMACS1, are common to all DMAC channels.

FIGURE 8-1:

TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS

CPU

SRAM

DMA RAM

CPU Peripheral DS Bus

Peripheral 3

DMA

Peripheral

Non-DMA

SRAM X-Bus

PORT 2

PORT 1

Peripheral 1

DMA

Ready

Peripheral 2

DMA

Ready

DMA DS Bus

CPU

DMA

CPU

DMA

CPU

DMA

Peripheral Indirect Address

Note: For clarity, CPU and DMA address buses are not shown.

DMA Controller

DMA

Channels

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