MCP1790T-3002ESLASHEB datasheet(17/34 Pages) MICROCHIP

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DS22075A-page 17

MCP1790/MCP1791

4.9

Power Good Output (PWRGD)

The MCP1791 has an open-drain Power Good

(PWRGD) output signal capable of sinking a minimum

of 5.0 mA of current while maintaining a PWRGD

output voltage of 0.4V or less.

As the output voltage of the LDO rises, the PWRGD

output will be held low until the output voltage has

exceeded the power good threshold (VPWRGD_TH) level

by an amount equal to the power good hysteresis value

((VPWRGD_HYS), typically 2% of VR. Once this threshold

has been exceeded, the power good output signal will

be pulled high by an external pull-up resistor, indicating

that the output voltage is stable and within regulation

limits.

If the output voltage of the LDO falls below the power

good threshold (VPWRGD_TH) level, the power good

output will transition low. The power good circuitry has

a 235 µs delay when detecting a falling output voltage,

which helps to increase noise immunity of the power

good output and avoid false triggering of the power

good output during fast output transients. See

Figure 4-4 for power good timing characteristics.

When the LDO is put into Shutdown mode using the

SHDN input, the power good output is pulled low within

400 ns typical, indicating that the output voltage will be

out of regulation. The timing diagram for the power

good output when using the shutdown input is shown in

Figure 4-5.

The PWRGD output may be pulled up to either VIN or

VOUT. When pulled to VOUT, the PWRGD output will

sink very little current during shutdown. When PWRGD

is pulled up to VIN , the PWRGD output will sink current

during shutdown. That is because VOUT is 0 during

shutdown while VIN is still active. When the PWRGD

output is pulled to VIN , the PWRGD output signal will

track VIN at startup until the threshold of the PWRGD

circuitry has been reached and the PWRGD circuitry

pulls the signal back low. Therefore, when pulling

PWRGD to VIN instead of VOUT, the designer must be

aware of the PWRGD signal going high while the input

voltage is rising at startup. Pulling PWRGD to VOUT

removes the startup pulse.

FIGURE 4-4:

Power Good Timing.

FIGURE 4-5:

Power Good Timing from

Shutdown.

TPG

TVDET_PWRGD

VPWRGD_TH

VOUT

PWRGD

VOL

VOH

VPWRGD_HYS

30 µs

235 µs

VIN

SHDN

VOUT

100 µs

TOR

PWRGD

TPG

CLOAD = 1.0 µF

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