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PIC18F13K50-E/SS Datasheet(PDF) 39 Page - Microchip Technology |
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PIC18F13K50-E/SS Datasheet(HTML) 39 Page - Microchip Technology |
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39 / 414 page  © 2009 Microchip Technology Inc. Preliminary DS41350C-page 37 PIC18F1XK50/PIC18LF1XK50 TABLE 3-2: REGISTER FILE SUMMARY (PIC18F1XK50/PIC18LF1XK50) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 279, 26 TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 279, 26 TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 279, 26 STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 279, 27 PCLATU — — — Holding Register for PC<20:16> ---0 0000 279, 26 PCLATH Holding Register for PC<15:8> 0000 0000 279, 26 PCL PC, Low Byte (PC<7:0>) 0000 0000 279, 26 TBLPTRU — — — Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ---0 0000 279, 50 TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR<15:8>) 0000 0000 279, 50 TBLPTRL Program Memory Table Pointer, Low Byte (TBLPTR<7:0>) 0000 0000 279, 50 TABLAT Program Memory Table Latch 0000 0000 279, 50 PRODH Product Register, High Byte xxxx xxxx 279, 61 PRODL Product Register, Low Byte xxxx xxxx 279, 61 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 0000 000x 279, 65 INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP — RABIP 1111 -1-1 279, 66 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 279, 67 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 279, 43 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 279, 43 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 279, 43 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 279, 43 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of FSR0 offset by W N/A 279, 43 FSR0H — — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000 279, 43 FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx 279, 43 WREG Working Register xxxx xxxx 279 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 279, 43 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 279, 43 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 279, 43 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 279, 43 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value of FSR1 offset by W N/A 279, 43 FSR1H — — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000 280, 43 FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx 280, 43 BSR — — — — Bank Select Register ---- 0000 280, 31 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 280, 43 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 280, 43 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 280, 43 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 280, 43 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of FSR2 offset by W N/A 280, 43 FSR2H — — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000 280, 43 FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx 280, 43 STATUS — — —N OV Z DC C ---x xxxx 280, 41 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See Section 23.4 “Brown-out Reset (BOR)”. 2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is read-only. 3: Bits RA0 and RA1 are available only when USB is disabled. |
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