PIC12F609-ESLASHP datasheet(165/212 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41302D-page 165

PIC12F609/615/617/12HV609/615

TABLE 16-12: PIC12F615/617/HV615 A/D CONVERSION REQUIREMENTS

FIGURE 16-10:

PIC12F615/617/HV615 A/D CONVERSION TIMING (NORMAL MODE)

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C

 TA  +125°C

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

AD130* TAD

A/D Clock Period

1.6

—

9.0

sTOSC-based, VREF 3.0V

3.0

—

9.0

sTOSC-based, VREF full range(3)

A/D Internal RC

Oscillator Period

3.0

6.0

9.0

s

ADCS<1:0> = 11 (ADRC mode)

At VDD = 2.5V

1.6

4.0

6.0

sAt VDD = 5.0V

AD131

TCNV

Conversion Time

(not including

Acquisition Time)(1)

—11

—

TAD

Set GO/DONE bit to new data in A/D

Result register

AD132* TACQ

Acquisition Time

11.5

—

s

AD133* TAMP

Amplifier Settling Time

—

s

AD134

TGO

Q4 to A/D Clock Start

—

TOSC/2

TOSC/2 +

TCY

—

If the A/D clock source is selected as

RC, a time of TCY is added before the

A/D clock starts. This allows the SLEEP

instruction to be executed.

These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1:

ADRESH and ADRESL registers may be read on the following TCY cycle.

See Section 10.3 “A/D Acquisition Requirements” for minimum conditions.

Full range for PIC12HV609/HV615 powered by the shunt regulator is the 5V regulated voltage.

AD131

AD130

BSF ADCON0, GO

A/D CLK

A/D Data

ADRES

ADIF

Sample

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

Note 1:

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP

instruction to be executed.

1 TCY

AD134

(TOSC/2(1))

1 TCY

AD132

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