PIC18F14K50-ESLASHSS datasheet(79/414 Pages) MICROCHIP

79 / 414 page

Preliminary

DS41350C-page 77

PIC18F1XK50/PIC18LF1XK50

8.0

LOW DROPOUT (LDO)

VOLTAGE REGULATOR

The

PIC18F1XK50

devices

differ

from

the

PIC18LF1XK50 devices due to an internal Low

Dropout (LDO) voltage regulator. The PIC18F1XK50

contain an internal LDO, while the PIC18LF1XK50 do

not.

The lithography of the die allows a maximum operating

voltage of the nominal 3.6V on the internal digital logic.

In order to continue to support 5.0V designs, a LDO

voltage regulator is integrated on the die. The LDO

voltage regulator allows for the internal digital logic to

operate at 3.3V, while I/O’s operate at 5.0V (VDD).

The LDO voltage regulator requires an external bypass

capacitor for stability. The VUSB pin is required to have

an external bypass capacitor. It is recommended that

the capacitor be a ceramic cap between 0.22 to 0.47 µF.

On power-up, the external capacitor will look like a

large load on the LDO voltage regulator. To prevent

erroneous operation, the device is held in Reset while

a constant current source charges the external

capacitor. After the cap is fully charged, the device is

released from Reset. For more information, refer to

Section 27.0 “Electrical Specifications”.

PIC18F14K50-E/SS Datasheet(PDF) 79 Page - Microchip Technology