MPC5200B_10 datasheet(54/72 Pages) FREESCALE

Part #	MPC5200B

Description	SDRAM/DDR Memory Controller

PDF	72 Pages

Scroll/Zoom	100%

Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

Logo

54 / 72 page

MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

Figure 44. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)

1.3.17

GPIOs and Timers

1.3.17.1

General and Asynchronous Signals

The MPC5200B contains several sets if I/Os that do not require special setup, hold, or valid requirements. Most of these are

asynchronous to the system clock. The following numbers are provided for test and validation purposes only, and they assume

a 133 MHz internal bus frequency.

Figure 45 shows the GPIO Timing Diagram. Table 50 gives the timing specifications.

Table 50. Asynchronous Signals

Sym

Description

Min

Max

Units

SpecID

tCK

Clock Period

7.52

—

A16.1

tIS

Input Setup

—

A16.2

tIH

Input Hold

—

A16.3

tDV

Output Valid

—

15.33

A16.4

tDH

Output Hold

—

A16.5

SCK

(CLKPOL=0)

SCK

(CLKPOL=1)

MOSI

Input

MISO

Output

MPC5200B Datasheet(PDF) 54 Page - Freescale Semiconductor, Inc

MPC5200B Datasheet(HTML) 54 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL