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HMC702LP6CE Datasheet(PDF) 39 Page - Hittite Microwave Corporation

Part # HMC702LP6CE
Description  14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER
PDF  46 Pages
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Manufacturer  HITTITE [Hittite Microwave Corporation]
Direct Link  http://www.hittite.com
Logo HITTITE - Hittite Microwave Corporation

HMC702LP6CE Datasheet(HTML) 39 Page - Hittite Microwave Corporation

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For price, delivery, and to place orders, please contact Hittite Microwave Corporation:
20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373
Order On-line at www.hittite.com
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Table 19. Reg 08h Charge Pump Trim & Offset Register
Bit
Type
Name
Default
Description
3:0
r/W
cp_UPtrim_sel
0
trim Up gain, 14.3ua lsb, binary, 100ua max
7:4
r/W
cp_Dntrim_sel
0
trim Dn gain, 14.3ua lsb, binary, 100ua max
11:8
r/W
cp_UPoffset_sel
4
Up offset leakage current, 28.7ua lsb, binary,
430ua max
15:12
r/W
cp_Dnoffset_sel
0
Dn offset leakage current, 28.7ua , binary,
430uamax
17:16
r/W
cp_amp_bias_sel
2
charge Pump Dummy Branch op amp bias
selection, 100ua
Table 20. Reg 09h Charge Pump EN Register
Bit
Type
Name
Default
Description
0
r/W
cp_pull_updn_en
0
enables cP UP/Down control reg09 [1]
1
r/W
cp_pull_dn_upb
0
0 - forces charge Pump Up when reg09[0]=1
1 - forces charge Pump Dn when reg09[0]=1
Table 21. Reg 0Ah VCO Auto Tune & Control Register
Bit
Type
Name
Default
Description
0
r/W
vcot_auto_start
0
enables auto start of Vco cap tuning when frac
word is written to spi
1
r/W
vcot_man_start
0
starts manual vco tuning when auto_start=0
(must be cleared to 0 before another tune)
5:2
r/W
vcot_ncyc_rdiv
2
exponent selection for number of rdiv cycles to
wait during measurement (effects time to perform
the measurement and hence the accuracy)
6
r/W
vcot_invert_outdata
0
inverts the vco tuning cap polarity
7
r/W
vcot_swap_outdata
0
swaps the cap tuning data (left-to-right)
8
r/W
vcot_force_data_en
0
force enable for the Vco tuning cap word -
obsolete
9
r/W
vcot_force_dblbuff_mode
0
enables double buffer for vco caps. caps will go
to the vco when dsm_frac reg is written
11:10
r/W
vcot_xrefdiv_sel
0
xref divider generate vco tuning calibration
clock, and Vco serial Port clock VscK from the
crystal input (see figure 10) . this divider affects
calibration time and accuracy, currently only
divby1 is supported
00-->div by 1
01-->div by 2 not supported
10-->div by 4 not supported
11-->div by 8 not supported
Table 22. Reg 0Bh VCO Tuning & Control Register
Bit
Type
Name
Default
Description
15:0
r/W
spivco_direct_data
0
Used to set Vco control settings Vco specific,
see Vco seriaL Port description
HMC702LP6CE
v05.0110
14 GHz 16-BIT FRACTIONAL-N SYNTHESIZER



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