P2V28S20ATP-8 datasheet(21/51 Pages) VML

21 / 51 page

128Mb Synchronous DRAM

JULY.2000

Rev.2.2

P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)

P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)

P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)

Page-20

BURST INTERRUPTION [ Read Interrupted by Read ]

Burst read operation can be interrupted by new read of any bank. Random column access is allowed READ to READ interval

is minimum 1 CLK..

CLK

Command

A0-9

A10

BA0,1

Qai0

Qaj1 Qbk0

Qbk1

Qaj0

Qbk2

Qal0

Qal1

Qal2

Qal3

READ READ

READ

A11

DQM control

Write control

CLK

Command

A0-9

A10

BA0,1

READ

Qai0

Write

Daj0

Daj1

Daj2

Daj3

DQM

A11

[ Read Interrupted by Write ]

Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ

should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1

cycle after WRITE assertion.

Read Interrupted by Read (BL=4, CL=3)

Read Interrupted by Write (BL=4, CL=3)

P2V28S20ATP-8 Datasheet(PDF) 21 Page - Vanguard International Semiconductor

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