WM2623CD datasheet(5/10 Pages) WOLFSON

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Production Data

WM2623

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 October 2000

SERIAL INTERFACE

NCS

SCLK

DIN

5 15

D12

D13

D14

D15

SUD

SUCSFS

SUC16CS

WHFS

SUFSCLK

SUC16FS

Figure 1 Timing Diagram

Test Conditions:

RL = 10k

Ω, CL = 100pF. VDD = 5V ±10%, VREF = 2.048V and VDD = 3V ±10%, VREF = 1.024V over recommended operating

free-air temperature range (unless noted otherwise).

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tSUCSFS

Setup time NCS low before falling FS edge.

tSUFS

Setup time FS low before first falling SCLK edge.

8ns

tSUC16FS

Setup time, 16

th falling SCLK edge after FS low on

which data bit D0 is sampled before rising edge of FS.

tSUC16CS

Setup time, 16

th rising SCLK edge (first after data bit

D0 sampled) before NCS rising edge. If FS is used

instead of the 16

th rising edge to update the DAC, this

setup time is between the FS rising edge and the NCS

rising edge.

tWH

Pulse duration, SCLK high.

tWL

Pulse duration, SCLK low.

tSUD

Setup time, data ready before SCLK falling edge.

8ns

tHD

Hold time, data held valid after SCLK falling edge.

5ns

tWHFS

Pulse duration, FS high.

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