NX2601 datasheet(21/25 Pages) MICROSEMI

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NX2601

Rev. 2.3

12/01/06

For electrolytic or POSCAP, R

C is typically

selected to be zero.

f2 is determined by the desired output voltage

f 2

f 1

REF

LDOOUT

REF

/(V

0.8V /(2.5V

0.8)

2.35k

×−

= Ω×

−

=Ω

Choose R

f2=2.34kΩ.

Current Limit for LDO

Current limit of LDO is achieved by sensing the

LDO feedback voltage. When LDO_FB pin is below 0.4V,

the IC goes into hiccup mode. The IC will turn off all the

channel (Channel 1 and Channel 2 ) for 2096 cycles and

start to restart system again.

Layout Considerations

The layout is very important when designing high

frequency switching converters. Layout will affect noise

pickup and can cause a good design to perform with

less than expected results.

There are two sets of components considered in

the layout which are power components and small sig-

nal components. Power components usually consist of

input capacitors, high-side MOSFET, low-side MOSFET,

inductor and output capacitors. A noisy environment is

generated by the power components due to the switch-

ing power. Small signal components are connected to

sensitive pins or nodes. A multilayer layout which in-

cludes power plane, ground plane and signal plane is

recommended .

Layout guidelines:

1. First put all the power components in the top

layer connected by wide, copper filled areas. The input

capacitor, inductor, output capacitor and the MOSFETs

should be close to each other as possible. This helps to

reduce the EMI radiated by the power loop due to the

high switching currents through them.

2. Low ESR capacitor which can handle input RMS

ripple current and a high frequency decoupling ceramic

cap which usually is 1uF

need to be practically touch-

ing the drain pin of the upper MOSFET, a plane connec-

tion is a must.

3. The output capacitors should be placed as close

as to the load as possible and plane connection is re-

quired.

4. Drain of the low-side MOSFET and source of

the high-side MOSFET need to be connected thru a plane

ans as close as possible. A snubber nedds to be placed

as close to this junction as possible.

5. Source of the lower MOSFET needs to be con-

nected to the GND plane with multiple vias. One is not

enough. This is very important. The same applies to the

output capacitors and input capacitors.

6. Hdrv and Ldrv pins should be as close to

MOSFET gate as possible. The gate traces should be

wide and short. A place for gate drv resistors is needed

to fine tune noise if needed.

7. Vcc capacitor, BST capacitor or any other by-

passing capacitor needs to be placed first around the IC

and as close as possible. The capacitor on comp to

GND or comp back to FB needs to be place as close to

the pin as well as resistor divider.

8. The output sense line which is sensing output

back to the resistor divider should not go through high

frequency signals.

9. All GNDs need to go directly thru via to GND

plane.

10. The feedback part of the system should be

kept away from the inductor and other noise sources,

and be placed close to the IC.

11. In multilayer PCB, separate power ground and

analog ground. These two grounds must be connected

together on the PC board layout at a single point. The

goal is to localize the high current path to a separate

loop that does not interfere with the more sensitive ana-

log control function.

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