WM8144-10CFTSLASHV datasheet(14/27 Pages) WOLFSON

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WM8144-10

Wolfson Microelectronics

Table 3: Bit Allocation Assignment

CDATA WORD 1

CDATA WORD 2

G11 G10 G9

G10 G9G8G7

G6G5G4G3

G2G1G0

O4O3O2O1

G10 G9G8G7

G6G5G4G3

G2G1G0

O3O2O1

DV O4

Table 4: Bit Range and Resolution Options

DVMODE PWP1 PWP0

No. of

offset

bits

offset range

No. of gain

bits

gain

range

gain

resolution

(LSB

steps)

DV bits

-8 : 7

0:2

0.25

-16 - 15

0:2

0.5

-32 - 31

0:2

-8 - 7

0:2

0.5

-16 : 15

0:2

Theory of Operation (contd.)

Data Valid Generation

The DV pin can be controlled to determine whether a DV

pulse will be generated for a particular pixel. For exam-

ple, if red pixels only are required the following DV pulse

can be generated.

OP[9:0]

Figure 9

Data Latch

Under control of the LATCHOP bit the output data bus

can be prevented from clamping until the next Data Valid

pulse. Hence the above output would become:

OP[9:0]

Figure 10

Output data interface

By default, data is output from the device as a ten-bit

wide word on OP[9:0]. Optionally, data can be output in

an eight-bit word format. Figure 11 shows this function.

Data is presented on pins OP[9:2] at twice pixel rate.

Figure 11: Eight-bit Multiplexed Bus Output

A = d9,d8,d7,d6,d5,d4,d3,d2

B = d1,d0,X,X,X,X,X,ORNG

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