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WM8191 Datasheet(PDF) 7 Page - Wolfson Microelectronics plc |
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WM8191 Datasheet(HTML) 7 Page - Wolfson Microelectronics plc |
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7 / 27 page  Advanced Information WM8191 WOLFSON MICROELECTRONICS LTD AI Rev 3.1 April 2001 7 INPUT VIDEO SAMPLING MCLK VSMP INPUT VIDEO t PER t MCLKH t MCLKL t VSMPSU t VSMPH t VSU t VH t RSU t RH Figure 1 Input Video Timing Test Conditions AVDD1 = AVDD2 = DVDD1 = 4.75 to 5.25V, DVDD2 = DVDD3 = 2.97 to 3.63V, AGND = DGND = 0V, TA = 0 to 70 °C, MCLK = 12MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS MCLK period tPER 83.3 ns MCLK high period tMCLKH 37.5 ns MCLK low period tMCLKL 37.5 ns VSMP set-up time tVSMPSU 10 ns VSMP hold time tVSMPH 5ns Video level set-up time tVSU 15 ns Video level hold time tVH 5ns Reset level set-up time tRSU 15 ns Reset level hold time tRH 5ns Notes: 1. tVSU and tRSU denote the set-up time required after the input video signal has settled. 2. Parameters are measured at 50% of the rising/falling edge. OUTPUT DATA TIMING MCLK OP[13:0] t PD Figure 2 Output Data Timing |
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