Production Data

WM8736

WOLFSON MICROELECTRONICS LTD

PD Rev 2.1 January 2001

7

DEVICE DESCRIPTION

WM8736 is a complete 6-channel stereo audio digital-to-analogue converter, including digital

interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and

output smoothing filters.

The device is implemented as three separate stereo DACs in a single package and controlled by a

single interface. Three separate data input pins are provided for each of the three separate stereo

DACs, and LRCIN, BCKIN and SCKI are shared between them.

Control of internal functionality of the device is by either hardware control (pin programmed) or

software control (serial interface). The MODE pin selects between hardware and software control. In

software control mode, an SPI type interface is used. This interface may be asynchronous to the

audio data interface. Control data will be re-synchronized to the audio processing internally.

Operation using system clock of 256fs, 384fs or 512fs is provided, selection between clock rates

being automatically controlled in hardware mode, or serial controlled when in software mode. Sample

rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate system clock is input.

The data interface supports normal (Japanese right justified) and I

delayed) interface formats, in both ‘packed’ and unpacked forms. When in hardware mode, the three

serial interface pins become control pins to allow selection of input data format type (I

input word length (16, 18, 20, or 24-bit) and de-emphasis function.

SYSTEM CLOCK

The system clock for WM8736 must be either 256fs, 384fs or 512fs, where fs is the audio sampling

frequency (LRCIN) typically 32kHz, 44.1kHz, 48 or 96kHz. The system clock is used to operate the

digital filters and the noise shaping circuits.

WM8736 has a system clock detection circuit that automatically determines what the system clock

frequency relative to the sampling rate is (to within +/- 8 system clocks). If greater than 8 clocks

error, then the interface shuts down the DAC and mutes the output. The system clock should be

synchronised with LRCIN, but WM8736 is tolerant of phase differences or jitter on this clock. Severe

distortion in the phase difference between LRCIN and the system clock will be detected, and cause

the device to automatically resynchronise. If the externally applied LRCIN slips in phase by more

than half the internal LRCIN period, which is derived from master clock, then the interface

resynchronises. Such a case would, for example, occur if repeated LRCIN clocks were received

with only 252 systems clocks per period. In this case the interface would only resynchronise once

every 64 LRCIN periods, even if jitter was present on the LRCIN signal. During resynchronisation,

the device will either repeat the previous sample, or drop the next sample, depending on the nature

of the phase slip. This will ensure no discernible “click“ at the analogue outputs during

resynchronisation. Table 1 shows the typical system clock frequency inputs for the WM8736.

SYSTEM CLOCK FREQUENCY (MHZ)

SAMPLING RATE

(LRCIN)

256fs

384fs

512fs

32kHz

8.192

12.288

16.384

44.1kHz

11.2896

16.9340

22.5792

48kHz

12.288

18.432

24.576

96kHz

24.576

36.864

Table 1 System Clock Frequencies Versus Sampling Rate

AUDIO DATA INTERFACE

The Serial Data interface to WM8736 is fully compatible with both normal (MSB first, right-justified) or

I

the number of data bits, i.e. normally 32 in 16-bit mode) or unpacked (more than 32 bit clocks per

LRCIN period).

The WM8736 will automatically detect 16-bit packed data being sent to the device in normal mode,

and accept the data in this input format accordingly.