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SS6341

After the initial transient, the ESL dependent term drops

off. Because of the strong relationship between output

capacitor ESR and output load transient, the output

capacitor is usually chosen for ESR, not for capacitance

value. A capacitor with suitable ESR will usually have a

larger capacitance value than is needed for energy

storage.

A common way to lower ESR and raise ripple current

capability is to parallel several capacitors. In most case,

multiple electrolytic capacitors of small case size are

better than a single large case capacitor.

Output Inductor Selection

The inductor value and type should be chosen based on

output slew rate requirement, output ripple requirement

and expected peak current, and is primarily controlled by

the required current response time. The SS6341 will

provide either 0% or 85% duty cycle in response to a load

transient. The response time to a transient is different for

the application of load and remove of load.

t

L

I

V

V

RISE

OUT

IN

OUT

=

×

−

∆

,

t

=

L

I

V

FALL

OUT

OUT

× ∆

where

In a typical 5V input, 2V output application, a 3

µH

inductor has a 1A/

µS rise time, resulting in a 5µS delay in

responding to a 5A load current step. To optimize

performance, different combinations of input and output

voltage and expected loads may require different inductor

values. A smaller value of inductor will improve the

transient response at the expense of increased output

ripple voltage and inductor core saturation rating.

Peak current in the inductor will be equal to the maximum

output load current plus half of inductor ripple current. The

ripple current is approximately equal to:

I

=

(V

V

)

V

L

V

RIPPLE

IN

OUT

OUT

IN

−

×

× ×

f

where f = 200KHz oscillator frequency.

The inductor must be able to withstand peak current

without saturation, and the copper resistance in the

winding should be kept as low as possible to minimize

resistive power loss

Input Capacitor Selection

Most of the input supply current is supplied by the input

bypass capacitor, and the resulting RMS current flow in

the input capacitor will heat it up. Use a mix of input bulk

capacitors to control the voltage overshoot across the

upper MOSFET. The ceramic capacitance for the high

frequency decoupling should be placed very close to the

upper MOSFET to suppress the voltage induced in the

parasitic circuit impedance. The buck capacitors to

supply the RMS current are approximate equal to:

I

(1 D)

D

I

1

12

V

D

f L

RMS

2

OUT

IN

2

= −

×

×

+

×

×

×









where

D

V

V

OUT

IN

=

The capacitor voltage rating should be at least 1.25 times

greater than the maximum input voltage.

PWM MOSFET Selection

In high current PWM application, the MOSFET power

dissipation, package type and heatsink are the dominant

design

factors.

The

conduction

loss

is

the

only

component of power dissipation for the lower MOSFET,

since it turns on into near zero voltage. The upper

MOSFET has conduction loss and switching loss. The

gate charge losses are proportional to the switching

frequency and are dissipated by the SS6341.

However, the gate charge increases the switching

switching losses. Ensure that both MOSFETs are within

their maximum junction temperature at high ambient

temperature

by

calculating

the

temperature

rise

according to package thermal resistance specifications.

P

I

R

D

I

V

t

f

2

UPPER

OUT

2

DS(ON)

OUT

IN

SW

=

×

× +

×

×

×

P

I

R

D)

LOWER

OUT

2

DS(ON)

=

×

× −

(1

The equations above do not model the power loss from the

reverse recovery of the lower MOSFET’s body diode.

Rev.2.01 6/26/2003