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PAM1707BZKB4 Datasheet(PDF) 67 Page - Texas Instruments |
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PAM1707BZKB4 Datasheet(HTML) 67 Page - Texas Instruments |
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67 / 155 page  EMB_CS EMB_CAS EMB_RAS EMB_WE EMB_CLK EMB_SDCKE EMB_BA[1:0] EMB_A[12:0] EMB_WE_DQM[0] EMB_D[15:0] EMIFB CE CAS RAS WE CLK CKE BA[1:0] A[12:0] LDQM DQ[15:0] SDRAM 4Mx16x4 Bank EMB_WE_DQM[1] UDQM EMB_WE_DQM[2] EMB_D[31:16] EMB_WE_DQM[3] CE CAS RAS WE CLK CKE BA[1:0] A[12:0] LDQM DQ[15:0] SDRAM 4Mx16x4 Bank UDQM AM1705 www.ti.com SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010 Figure 6-18. EMIFB to Dual 4M × 16 × 4 bank SDRAM Interface Table 6-22. Example of 16-bit EMIFB Address Pin Connections SDRAM Size Width Banks Address Pins 64M bits ×16 4 SDRAM A[11:0] EMIFB EMB_A[11:0] 128M bits ×16 4 SDRAM A[11:0] EMIFB EMB_A[11:0] 256M bits ×16 4 SDRAM A[12:0] EMIFB EMB_A[12:0] 512M bits ×16 4 SDRAM A[12:0] EMIFB EMB_A[12:0] Table 6-23 is a list of the EMIFB registers. Table 6-23. EMIFB Controller Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0xB000 0000 MIDR Module ID Register 0xB000 0008 SDCFG SDRAM Configuration Register 0xB000 000C SDRFC SDRAM Refresh Control Register 0xB000 0010 SDTIM1 SDRAM Timing Register 1 0xB000 0014 SDTIM2 SDRAM Timing Register 2 0xB000 001C SDCFG2 SDRAM Configuration 2 Register 0xB000 0020 BPRIO Peripheral Bus Burst Priority Register Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 67 Submit Documentation Feedback Product Folder Link(s): AM1705 |
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