CS5530

DS742F3

9

SWITCHING CHARACTERISTICS

(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0

Notes: 21. Device parameters are specified with a 4.9152 MHz clock.

22. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

23. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an

external clock source.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

(Note 21)

External Clock or Crystal Oscillator

MCLK

1

4.9152

5

MHz

Master Clock Duty Cycle

40

-

60

%

Rise Times

(Note 22)

Any Digital Input Except SCLK

SCLK

Any Digital Output

-

-

-

-

-

50

1.0

100

-

µs

µs

ns

Fall Times

(Note 22)

Any Digital Input Except SCLK

SCLK

Any Digital Output

-

-

-

-

-

50

1.0

100

-

µs

µs

ns

Start-up

Oscillator Start-up Time

XTAL = 4.9152 MHz

(Note 23)

-20-

ms

Serial Port Timing

Serial Clock Frequency

SCLK

0

-

2

MHz

Serial Clock

Pulse Width High

Pulse Width Low

250

250

-

-

-

-

ns

ns

SDI Write Timing

CS Enable to Valid Latch Clock

50

-

-

ns

Data Set-up Time prior to SCLK rising

50

-

-

ns

Data Hold Time After SCLK Rising

100

-

-

ns

SCLK Falling Prior to CS Disable

100

-

-

ns

SDO Read Timing

CS to Data Valid

--

150

ns

SCLK Falling to New Data Bit

--

150

ns

CS Rising to SDO Hi-Z

--

150

ns