P89LPC9301FDH datasheet(8/65 Pages) NXP

8 / 65 page

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

8 of 65

NXP Semiconductors

P89LPC9301/931A1

8-bit microcontroller with accelerated two-clock 80C51 core

P0.6/CMP1/KBI6

I/O

P0.6 — Port 0 bit 6. High current source.

CMP1 — Comparator 1 output.

KBI6 — Keyboard input 6.

P0.7/T1/KBI7

I/O

P0.7 — Port 0 bit 7. High current source.

I/O

T1 — Timer/counter 1 external count input or overﬂow output.

KBI7 — Keyboard input 7.

P1.0 to P1.7

I/O, I

[1]

Port 1: Port 1 is an 8-bit I/O port with a user-conﬁgurable output type, except for

three pins as noted below. During reset Port 1 latches are conﬁgured in the input

only mode with the internal pull-up disabled. The operation of the conﬁgurable

Port 1 pins as inputs and outputs depends upon the port conﬁguration selected.

Each of the conﬁgurable port pins are programmed independently. Refer to

Section 7.16.1 “Port conﬁgurations” and Table 10 “Static characteristics” for

details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt trigger inputs.

Port 1 also provides various special functions as described below:

P1.0/TXD

I/O

P1.0 — Port 1 bit 0.

TXD — Transmitter output for serial port.

P1.1/RXD

I/O

P1.1 — Port 1 bit 1.

RXD — Receiver input for serial port.

P1.2/T0/SCL

I/O

P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O

T0 — Timer/counter 0 external count input or overﬂow output (open-drain when

used as output).

I/O

SCL — I2C-bus serial clock input/output.

P1.3/INT0/SDA

I/O

P1.3 — Port 1 bit 3 (open-drain when used as output).

INT0 — External interrupt 0 input.

I/O

SDA — I2C-bus serial data input/output.

P1.4/INT1

I/O

P1.4 — Port 1 bit 4. High current source.

INT1 — External interrupt 1 input.

P1.5/RST

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during power-on or if selected via UCFG1. When

functioning as a reset input, a LOW on this pin resets the microcontroller, causing

I/O ports and peripherals to take on their default states, and the processor begins

execution at address 0. Also used during a power-on sequence to force ISP mode.

P1.6

I/O

P1.6 — Port 1 bit 6. High current source.

P1.7

I/O

P1.7 — Port 1 bit 7. High current source.

P2.0 to P2.7

I/O

Port 2: Port 2 is an 8-bit I/O port with a user-conﬁgurable output type. During reset

Port 2 latches are conﬁgured in the input only mode with the internal pull-up

disabled. The operation of Port 2 pins as inputs and outputs depends upon the

port conﬁguration selected. Each port pin is conﬁgured independently. Refer to

Section 7.16.1 “Port conﬁgurations” and Table 10 “Static characteristics” for

details.

All pins have Schmitt trigger inputs.

Port 2 also provides various special functions as described below:

P2.0

I/O

P2.0 — Port 2 bit 0.

P2.1

I/O

P2.1 — Port 2 bit 1.

Table 3.

Pin description …continued

Symbol

Type Description

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