PCA9516A_3

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 — 23 April 2009

5 of 19

NXP Semiconductors

PCA9516A

6.

Functional description

systems to be expanded with only one repeater delay and no functional degradation of

system performance.

The PCA9516A contains five bidirectional, open-drain buffers specifically designed to

arbitration or clock stretching, the PCA9516A acts like five pairs of non-inverting,

open-drain buffers, one for SDA and one for SCL. Refer to Figure 1 “Block diagram”.

6.1 Enable

The enable pins EN1 through EN4 are active HIGH and have internal pull-up resistors.

Each enable pin ENn controls its associated SDAn and SCLn ports. When LOW, the ENn

pin blocks the inputs from SDAn and SCLn as well as disabling the output drivers on the

SDAn and SCLn pins. The enable pins should only change state when both the global bus

and the local port are in an idle state to prevent system failures.

The active HIGH enable pins allow the use of open-drain drivers which can be wire-ORed

to create a distributed enable where either centralized control signal (master) or spoke

signal (submaster) can enable the channel when it is idle.

The size of these pull-up resistors depends on the system, but each side of the repeater

must have a pull-up resistor. This part is designed to work with Standard-mode and

only specify 3 mA output drive; this limits the termination current to 3 mA in a generic

see application note

information on sizing resistors and precautions when using more than one

PCA9515A/PCA9516A in a system or using the PCA9515A/PCA9516A in conjunction

with the P82B96.

7.

Application design-in information

A typical application is shown in Figure 5. In this example, the system master is running

unless slave 3 is isolated, and then the master bus and slave 1 and slave 2 can run at

400 kHz.

Any segment of the hub can talk to any other segment of the hub. Bus masters and slaves

can be located on all five segments with 400 pF load allowed on each segment.

Unused ports should be isolated by holding the enable pin (ENn) to GND and/or pulling

normally connected to SDA0/SCL0. If the SDA0/SCL0 port is not used, the pins need to