PCA9533_3

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 — 27 April 2009

10 of 24

NXP Semiconductors

PCA9533

7.4 Bus transactions

Fig 11. Write to register

0

A

S

slave address (PCA9533/01)

START condition

R/W

acknowledge

from slave

002aae629

0

0

AI

0

B2B1B0

0

command byte

A

acknowledge

from slave

12345678

SCL

9

SDA

DATA 1

A

write to register

data out from port

acknowledge

from slave

DATA 1 VALID

data to register

100010

1

Fig 12. Read from register

1000100

A

S1

START condition

R/W

acknowledge

from slave

002aae630

A

acknowledge

from slave

SDA

A

P

acknowledge

from master

data from register

DATA (first byte)

slave address (PCA9533/01)

STOP

condition

S

(repeated)

START condition

(cont.)

(cont.)

1

A

R/W

acknowledge

from slave

slave address (PCA9533/01)

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

NA

no acknowledge

from master

data from register

DATA (last byte)

command byte

0

0

AI

0

B2 B1

0B0

Auto-Increment

register address

if AI = 1

100010

1

Remark: This figure assumes the command byte has previously been programmed with 00h.

Fig 13. Read input port register

1000101

A

S1

START condition

R/W

acknowledge

from slave

002aae631

A

acknowledge

from master

SDA

NA

read from

port

data into

port

P

data from port

no acknowledge

from master

data from port

DATA 4

slave address (PCA9533/01)

DATA 1

STOP

condition

DATA 2

DATA 3

DATA 4

DATA 1