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PCA9558PW Datasheet(PDF) 13 Page - NXP Semiconductors

Part # PCA9558PW
Description  8-bit I2C-bus and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C-bus EEPROM DIP switch and 2-kbit EEPROM
PDF  27 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA9558PW Datasheet(HTML) 13 Page - NXP Semiconductors

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PCA9558_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 April 2009
13 of 27
NXP Semiconductors
PCA9558
8-bit I2C-bus/SMBus I/O port
7.1.3.5
256-byte EEPROM write to GPIO
A mode is available whereby a byte of data in the 256-byte EEPROM array can be written
to the GPIO (OP register). This is initiated by the I2C-bus. In this mode, a control word
indicating a read from the 256-byte EEPROM and write to the GPIO is sent, followed by
the word address of the data within the EEPROM array. Upon Acknowledge from the
slave, the data is sent to the GPIO. See Figure 16.
7.1.3.6
256-byte EEPROM write from GPIO
A mode is available whereby data in the GPIO (IP register) can be written to the 256-byte
EEPROM. This is initiated by the I2C-bus. In this mode, a control word indicating a read
from the GPIO and write to the 256-byte EEPROM is sent, followed by the word address
for the data to be written. Once the slave has sent an Acknowledge, the master must send
a STOP condition. See Figure 17.
After the STOP condition, the E/W cycle starts, and the parts will not respond to any
request to access the EEPROM array until the cycle finishes, approximately 4 ms.
M bytes where M
≥ 1.
Fig 15. I2C-bus read operation from 256-byte EEPROM
00111
A0
0
A
S1
START condition
R/W
002aad379
A
acknowledge
from slave
P
slave address
STOP
condition
command code
000001
01
(cont.)
(cont.)
EEPROM address
A
acknowledge
from slave
DATA N
DATA N + M
A
acknowledge
from master
Auto-Increment
word address
NA
no acknowledge
from master
Auto-Increment
word address
00111
A0
1
1
R/W
slave address
A
acknowledge
from slave
S
(re)START condition
acknowledge
from slave
See Table 3 for the needed command code.
Fig 16. Read from 256-byte EEPROM and write to GPIO registers
00111
A0
0
A
S1
START condition
R/W
acknowledge
from slave
002aad380
A
acknowledge
from slave
P
slave address
STOP condition;
data latched into
GPIO register
NA
no acknowledge
from master
data from 256-byte EEPROM
command byte
0
0
xxxx
0x
d6 d5 d4 d3 d2 d1 d0
00111
A0
1
A
S1
(re)START
condition
R/W
acknowledge
from slave
slave address
(cont.)
(cont.)
d7
EEPROM address
a6 a5 a4 a3 a2 a1 a0
a7
A
acknowledge
from slave



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