PCA9575 datasheet(13/38 Pages) NXP

13 / 38 page

PCA9575_3

Product data sheet

Rev. 03 — 9 November 2009

13 of 38

NXP Semiconductors

PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.6.6 Register 5 - Bus-hold/pull-up/pull-down enable 1 register

Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins.

Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 1. In this mode, the

pull-up/pull-downs will be disabled for I/O bank 1. Setting the bit 0 to logic 0 disables

bus-hold feature.

Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.

Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 7. Setting

the bit 1 to logic 0 disables pull-up/pull-downs on the I/O bank 1 pins and contents of

Table 9.

bit description

Legend: * default value.

Bit

Symbol

Access

Value

Description

E1.7

R/W

not used

E1.6

R/W

E1.5

R/W

E1.4

R/W

E1.3

R/W

E1.2

R/W

E1.1

R/W

allows the user to enable/disable pull-up/pull-downs on the

I/O bank 1 pins

0 = disables pull-up/pull-downs on the I/O bank 1 pins and

contents of Register 7 will have no effect on the I/O bank 0

(default value)

1 = enables selection of pull-up/pull-down using Register 7

E1.0

R/W

allows user to enable/disable the bus-hold feature for the

I/O bank 1 pins

0 = disables bus-hold feature (default value)

1 = enables bus-hold feature

PCA9575 Datasheet(PDF) 13 Page - NXP Semiconductors

PCA9575 Datasheet(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL