PCF8578HSLASH1 datasheet(21/46 Pages) NXP

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PCF8578_6

Product data sheet

Rev. 06 — 5 May 2009

21 of 46

NXP Semiconductors

PCF8578

LCD row/column driver for dot matrix graphic displays

master receiver must signal an end of data to the slave transmitter, by not generating an

acknowledge on the last byte clocked out of the slave. The slave transmitter then leaves

the data line HIGH, enabling the master to generate a STOP condition (P).

Display bytes are written into, or read from the RAM at the address speciﬁed by the data

pointer and subaddress counter. Both the data pointer and subaddress counter are

automatically incremented, enabling a stream of data to be transferred either to, or from

the intended devices.

In multiple device applications, the hardware subaddress pins of the PCF8579s (A0 to A3)

are connected to VSS or VDD to represent the desired hardware subaddress code. If two or

more devices share the same slave address, then each device must be allocated to a

unique hardware subaddress.

8.9 Display RAM

The PCF8578 contains a 32

× 40-bit static RAM which stores the display data. The RAM

is divided into 4 banks of 40 bytes (4

× 8 × 40 bits). During RAM access, data is

transferred to and from the RAM via the I2C-bus. The ﬁrst eight columns of data (0 to 7)

cannot be displayed but are available for general data storage and provide compatibility

with the PCF8579. There is a direct correspondence between X-address and column

output number.

8.9.1 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows an individual data byte or a series of data bytes to be written into, or read from, the

display RAM, controlled by commands sent on the I2C-bus.

8.9.2 Subaddress counter

The storage and retrieval of display data is dependent on the content of the subaddress

counter. Storage takes place only when the contents of the subaddress counter match

with the hardware subaddress. The hardware subaddress of the PCF8578, valid in mixed

mode only, is ﬁxed at 0000.

8.10 Command decoder

The command decoder identiﬁes command bytes that arrive on the I2C-bus.

The ﬁve commands available to the PCF8578 are deﬁned in Table 9.

The most-signiﬁcant bit of a command is the continuation bit C (see Table 10 and

Figure 16). Commands are transferred in WRITE mode only.

Table 9.

Deﬁnition of PCF8578 commands

Command

Operation code

Reference

Bit

set-mode

E[1:0]

M[1:0]

Table 11

set-start-bank

11111

B[1:0]

Table 12

device-select

A[3:0]

Table 13

RAM-access

G[1:0]

Y[1:0]

Table 14

load-X-address

X[5:0]

Table 15

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