Rev 1.00

March 22, 2010

19

HT45B0K

SPI to USB Bridge

USB Interrupt Structure

Several individual USB conditions can generate a USB interrupt. These conditions are the USB

suspended, USB resume, USB reset and USB endpoint FIFO access events. When the USB

interrupt caused by any of these conditions occurs, a low pulse will be generated on the INT line to

get the attention of the microcontroller or microprocessor.

For the USB Endpoint FIFO access event, there are the corresponding indication flags to indicate

which endpoint FIFO is accessed. As the Endpoint FIFO access flag is set, it will generate a USB

interrupt on INT line if the associated Endpoint FIFO pipe and interrupt control are both enabled.

The Endpoint FIFO access flags should be cleared by the application program. As the USB

suspended, USB resume or USB reset condition occurs, the corresponding indication flag, known

as SUSP, RESUME and URST bits, will be set and a USB interrupt will directly generated without

any associated interrupt control being enabled. The SUSP, RESUME and URST bits are read only

and set or cleared by the USB SIE.

S u s p e n d i n d i c a t i o n f l a g

S U S P

R e s u m e i n d i c a t i o n f l a g

R E S U M E

E U n I

R e s e t i n d i c a t i o n f l a g

U R S T

E n d p o i n t F I F O a c c e s s

i n d i c a t i o n f l a g E P n I F

E P n E

U S C R e g i s t e r

U S R R e g i s t e r

0

1

0

1

U I C R e g i s t e r

P I P E R e g i s t e r

I N T

USB Interrupt Structure