HT86A72 datasheet(33/68 Pages) HOLTEK

33 / 68 page

HT86Axx/HT86ARxx

Rev. 1.00

March 19, 2010

Interrupt Priority

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In case of simultaneous requests, the

accompanying table shows the priority that is applied.

Interrupt Source

Interrupt Vector Priority

External Interrupt

04H

Timer 0 Overflow

08H

Timer 1 Overflow

0CH

Timer 2 Overflow

10H

Timer 3 Overflow

14H

A/D Converter Overflow

18H

In cases where both external the timer interrupts are en-

abled and where an external and timer interrupt occur

simultaneously, the external interrupt will always have

priority and will therefore be serviced first. Suitable

masking of the individual interrupts using the INTC and

INTCH registers can prevent simultaneous occur-

rences.

External Interrupt

Each device contains a single external interrupt function

controlled by the external pin, INT. For an external inter-

rupt to occur, the corresponding external interrupt en-

able bit must be first set. This is bit 1 of the INTC register

and known as EEI. An external interrupt is triggered by

an external edge transition on the external interrupt pin

INT, after which the related interrupt request flag, EIF,

which is bit 4 of INTC, will be set. A configuration option

exists for the external interrupt pin to determine the type

of external edge transition which will trigger an external

interrupt. There are two options available, a low going

edge or both high and low going edges. When the mas-

ter interrupt and external interrupt bits are enabled, the

stack is not full and an active edge transition, as setup in

the configuration options, occurs on the INT pin, a sub-

routine call to the corresponding external interrupt vec-

tor, which is located at 04H, will occur. After entering the

interrupt execution routine, the corresponding interrupt

request flag, EIF, will be reset and the EMI bit will be

cleared to disable other interrupts.

Timer Interrupt

For a timer generated interrupt to occur, the correspond-

ing timer interrupt enable bit must be first set. Each de-

vice contains four 8-bit timers whose corresponding

interrupt enable bits are known as ET0I, ET1I, ET2I and

ET3I and are located in the INTC and INTCH registers.

Each timer also has a corresponding timer interrupt re-

quest flag, which are known as T0F, T1F, T2F and T3F,

also located in the INTC and INTCH registers. When the

master interrupt and corresponding timer interrupt en-

able bits are enabled, the stack is not full, and when the

corresponding timer overflows a subroutine call to the

corresponding timer interrupt vector will occur. The cor-

responding Program Memory vector locations for Timer

0, Timer1, Timer 2 and Timer 3 are 08H, 0CH, 10H and

14H. After entering the interrupt execution routine, the

corresponding interrupt request flags, T0F, T1F, T2F or

T3F will be reset and the EMI bit will be cleared to dis-

able other interrupts.

A/D Converter Interrupt

The internal A/D Converter interrupt is initialised by set-

ting the A/D interrupt request flag (ADF:bit6 of INTCH).

When the interrupt is enabled, and the stack is not full

and the ADF bit is set, a subroutine call to location

²18H²

will occur. The related interrupt request flag, ADF, will be

reset and the EMI bit cleared to disable further interrupts.

Programming Considerations

By disabling the interrupt enable bits, a requested inter-

rupt can be prevented from being serviced, however,

once an interrupt request flag is set, it will remain in this

condition in the INTC or INTCH register until the corre-

sponding interrupt is serviced or until the request flag is

cleared by a software instruction.

It is recommended that programs do not use the

²CALL

subroutine

² instruction within the interrupt subroutine.

Interrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications. If

only one stack is left and the interrupt is not well con-

trolled, the original control sequence will be damaged

once a

²CALL subroutine² is executed in the interrupt

subroutine.

All of these interrupts have the capability of waking up

the MCU when in the Power Down Mode. Only the Pro-

gram Counter is pushed onto the stack. If the contents of

the register or status register are altered by the interrupt

service program, which may corrupt the desired control

sequence, then the contents should be saved in ad-

vance.

HT86A72 Datasheet(PDF) 33 Page - Holtek Semiconductor Inc

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