PIC16LF707-ESLASHML datasheet(80/284 Pages) MICROCHIP

80 / 284 page

PIC16F707/PIC16LF707

DS41418A-page 80

Preliminary

 2010 Microchip Technology Inc.

9.1

ADC Configuration

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• Results formatting

9.1.1

PORT CONFIGURATION

The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O

pin should be configured for analog by setting the

associated TRIS and ANSEL bits. Refer to Section 6.0

“I/O Ports” for more information.

9.1.2

CHANNEL SELECTION

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 9.2

“ADC Operation” for more information.

9.1.3

ADC VOLTAGE REFERENCE

The ADREF bits of the ADCON1 register provides

control of the positive voltage reference. The positive

voltage reference can be either VDD, an external

voltage source or the internal Fixed Voltage Reference.

The negative voltage reference is always connected to

the ground reference. See Section 10.0 “Fixed

Voltage Reference” for more details on the Fixed

Voltage Reference.

9.1.4

CONVERSION CLOCK

The source of the conversion clock is software select-

able via the ADCS bits of the ADCON1 register. There

are seven possible clock options:

•FOSC/2

•FOSC/4

•FOSC/8

•FOSC/16

•FOSC/32

•FOSC/64

•FRC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One full 8-bit conversion requires 10 TAD periods

as shown in Figure 9-2.

For

correct

conversion,

the

appropriate

TAD

specification must be met. Refer to the A/D conversion

requirements

Section 25.0

“Electrical

Specifications” for more information. Table 9-1 gives

examples of appropriate ADC clock selections.

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC

clock

frequency,

which

may

adversely affect the ADC result.

TABLE 9-1:

ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

ADC Clock Period (TAD)

Device Frequency (FOSC)

ADC

Clock Source

ADCS<2:0>

20 MHz

16 MHz

8 MHz

4 MHz

1 MHz

Fosc/2

000

100 ns(2)

125 ns(2)

250 ns(2)

500 ns(2)

2.0

s

Fosc/4

100

200 ns(2)

250 ns(2)

500 ns(2)

1.0

s4.0 s

Fosc/8

001

400 ns(2)

0.5

s(2)

1.0

s2.0 s

8.0

s(3)

Fosc/16

101

800 ns

1.0

s2.0 s4.0 s

16.0

s(3)

Fosc/32

010

1.6

s2.0 s4.0 s

8.0

s(3)

32.0

s(3)

Fosc/64

110

3.2

s4.0 s

8.0

s(3)

16.0

s(3)

64.0

s(3)

FRC

x11

1.0-6.0

s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1:

The FRC source has a typical TAD time of 1.6

s for VDD.

These values violate the minimum required TAD time.

For faster conversion times, the selection of another clock source is recommended.

When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be performed during Sleep.

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