PIC16F707T-ESLASHML datasheet(105/284 Pages) MICROCHIP

105 / 284 page

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 105

PIC16F707/PIC16LF707

13.8

Timer1/3 Operation During Sleep

Timer1/3 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

• TMRxON bit of the TxCON register must be set

• TMRxIE bit of the PIEx register must be set

• PEIE bit of the INTCON register must be set

• TxSYNC bit of the TxCON register must be set

• TMRxCS bits of the TxCON register must be

configured

• T1OSCEN bit of the T1CON register must be

configured

• TMRxGIE bit of the TxGCON register must be

configured

The device will wake-up on an overflow and execute

the next instructions. If the GIE bit of the INTCON

Routine (0004h).

13.9

CCP Capture/Compare Time Base

(Timer1 Only)

The CCP module uses the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L

In Compare mode, an event is triggered when the value

CCPR1H:CCPR1L register pair matches the value in

the TMR1H:TMR1L register pair. This event can be a

Special Event Trigger.

For more information, see Section 17.0 “Capture/

Compare/PWM (CCP) Module”.

13.10 CCP Special Event Trigger

(Timer1 only)

When the CCP is configured to trigger a special event,

the trigger will clear the TMR1H:TMR1L register pair.

This special event does not cause a Timer1 interrupt.

The CCP module may still be configured to generate a

CCP interrupt.

In this mode of operation, the CCPR1H:CCPR1L

Timer1 should be synchronized to the FOSC/4 to utilize

the Special Event Trigger. Asynchronous operation of

Timer1 can cause a Special Event Trigger to be

missed.

In the event that a write to TMR1H or TMR1L coincides

with a Special Event Trigger from the CCP, the write will

take precedence.

For more information, see Section 17.2.4 “Special

Event Trigger”.

FIGURE 13-2:

TIMER1/TIMER3 INCREMENTING EDGE

TxCKI = 1

when TMR1/3

Enabled

TxCKI = 0

when TMR1/3

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

PIC16F707T-E/ML Datasheet(PDF) 105 Page - Microchip Technology

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