PIC16F1824-ESLASHML datasheet(367/420 Pages) MICROCHIP

367 / 420 page

 2010 Microchip Technology Inc.

Preliminary

DS41419A-page 367

PIC16F/LF1824/1828

TABLE 29-2:

OSCILLATOR PARAMETERS

TABLE 29-3:

PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V)

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C

TA +125°C

Param

No.

Sym.

Characteristic

Freq.

Tolerance

Min.

Typ†

Max.

Units

Conditions

OS08

HFOSC

Internal Calibrated HFINTOSC

Frequency(2)

2%

—

16.0

—

MHz

0°C

 TA  +60°C, VDD  2.5V

3—

16.0

—

MHz

60°C

 TA  +85°C, VDD 

2.5V

5%

—

16.0

—

MHz

-40°C

 TA  +125°C

OS08A MFOSC

Internal Calibrated MFINTOSC

Frequency(2)

2%

—

500

—

kHz

0°C

 TA  +60°C, VDD  2.5V

3%

—

500

—

kHz

60°C

 TA  +85°C, VDD 

2.5V

5%

—

500

—

kHz

-40°C

 TA  +125°C

OS10*

TIOSC ST HFINTOSC

Wake-up from Sleep Start-up Time

MFINTOSC

Wake-up from Sleep Start-up Time

—

s

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current

consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an

external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1

F and 0.01 F values in parallel are recommended.

3: By design.

Param

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

F10

FOSC Oscillator Frequency Range

—

MHz

F11

FSYS

On-Chip VCO System Frequency

—

MHz

F12

TRC

PLL Start-up Time (Lock Time)

—

F13*

CLK CLKOUT Stability (Jitter)

-0.25%

—

+0.25%

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3V, 25

C unless otherwise stated. These parameters are for design guidance

only and are not tested.

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