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PIC16F1824-E/ML Datasheet(PDF) 371 Page - Microchip Technology

Part # PIC16F1824-E/ML
Description  14/20-Pin Flash Microcontrollers with nanoWatt XLP Technology
PDF  420 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F1824-E/ML Datasheet(HTML) 371 Page - Microchip Technology

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 2010 Microchip Technology Inc.
Preliminary
DS41419A-page 371
PIC16F/LF1824/1828
TABLE 29-5:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
FIGURE 29-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C
TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ† Max. Units
Conditions
30
TMCLMCLR Pulse Width (low)
2
5
—
—
—
—
s
s
VDD = 3.3-5V, -40°C to +85°C
VDD = 3.3-5V
31
TWDTLP Low-Power Watchdog Timer
Time-out Period (No Prescaler)
10
18
27
ms
VDD = 3.3V-5V
32
TOST
Oscillator Start-up Timer Period(1), (2)
—
1024
—
Tosc (Note 3)
33*
TPWRT
Power-up Timer Period, PWRTE = 0
40
65
140
ms
34*
TIOZ
I/O high-impedance from MCLR Low
or Watchdog Timer Reset
——
2.0
s
35
VBOR
Brown-out Reset Voltage
2.38
1.80
2.5
1.9
2.65
2.05
VBORV=2.5V
BORV=1.9V
36*
VHYST
Brown-out Reset Hysteresis
0
25
50
mV
-40°C to +85°C
37*
TBORDC Brown-out Reset DC Response
Time
135
sVDD  VBOR
*
These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1
F and 0.01 F values in parallel are recommended.
T0CKI
T1CKI
40
41
42
45
46
47
49
TMR0 or
TMR1



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