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PIC18F23K20-E/ML Datasheet(PDF) 288 Page - Microchip Technology |
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PIC18F23K20-E/ML Datasheet(HTML) 288 Page - Microchip Technology |
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288 / 456 page ![]() PIC18F2XK20/4XK20 DS41303G-page 288 2010 Microchip Technology Inc. TABLE 20-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 62 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 62 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — — —63 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 61 CVRCON2 FVREN FVRST — — — — — —61 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 59 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 62 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 62 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 62 PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 62 LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 62 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 62 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. |
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