PIC18F23K20-ESLASHML datasheet(291/456 Pages) MICROCHIP

291 / 456 page

 2010 Microchip Technology Inc.

DS41303G-page 291

PIC18F2XK20/4XK20

FIGURE 21-2:

VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER

R/W-0

CVREN

CVROE(1)

CVRR

CVRSS

CVR3

CVR2

CVR1

CVR0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

CVREN: Comparator Voltage Reference Enable bit

=CVREF circuit powered on

=CVREF circuit powered down

bit 6

CVROE: Comparator VREF Output Enable bit(1)

=CVREF voltage level is also output on the CVREF pin

=CVREF voltage is disconnected from the CVREF pin

bit 5

CVRR: Comparator VREF Range Selection bit

= 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)

=0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)

bit 4

CVRSS: Comparator VREF Source Selection bit

= Comparator reference source, CVRSRC = (VREF+) – (VREF-)

= Comparator reference source, CVRSRC = VDD – VSS

bit 3-0

CVR<3:0>: Comparator VREF Value Selection bits (0

 (CVR<3:0>)  15)

When CVRR = 1:

CVREF = ((CVR<3:0>)/24)

 (CVRSRC) + VREF-

When CVRR = 0:

CVREF = (CVRSRC/4) + ((CVR<3:0>)/32)

 (CVRSRC) + VREF-

Note 1:

CVROE overrides the TRISA<2> bit setting.

Buffered CVREF Output

–

CVREF

Module

Voltage

Reference

Output

Impedance

R(1)

CVREF

Note

R is dependent upon the voltage reference Configuration bits, CVR<3:0> and CVRR.

PIC18F2XK20/4XK20

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