PIC18F23K20-ESLASHML datasheet(393/456 Pages) MICROCHIP

393 / 456 page

 2010 Microchip Technology Inc.

DS41303G-page 393

PIC18F2XK20/4XK20

FIGURE 26-13:

EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

75, 76

MSb

MSb In

bit 6 - - - - - -1

LSb In

bit 6 - - - -1

LSb

Note:

Refer to Figure 26-4 for load conditions.

Param.

No.

Symbol

Characteristic

Min

Max Units

Conditions

TscH

SCK Input High Time

(Slave mode)

Continuous

1.25 TCY + 30

—

71A

Single Byte

—

(Note 1)

TscL

SCK Input Low Time

(Slave mode)

Continuous

1.25 TCY + 30

—

72A

Single Byte

—

(Note 1)

TdiV2scH,

TdiV2scL

Setup Time of SDI Data Input to SCK Edge

100

—

73A

Tb2b

Last Clock Edge of Byte 1 to the 1st Clock Edge

of Byte 2

1.5 TCY + 40

—

(Note 2)

TscH2diL,

TscL2diL

Hold Time of SDI Data Input to SCK Edge

100

—

TdoR

SDO Data Output Rise Time

—

TdoF

SDO Data Output Fall Time

—

TscR

SCK Output Rise Time

(Master mode)

—25

TscF

SCK Output Fall Time (Master mode)

—

TscH2doV,

TscL2doV

SDO Data Output Valid after SCK Edge

—

TdoV2scH,

TdoV2scL

SDO Data Output Setup to SCK Edge

TCY

—ns

Note 1:

Requires the use of Parameter #73A.

Only if Parameter #71A and #72A are used.

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