PIC18F23K20-ESLASHML datasheet(394/456 Pages) MICROCHIP

394 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 394

 2010 Microchip Technology Inc.

FIGURE 26-14:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)

Param

No.

Symbol

Characteristic

Min

Max Units Conditions

TssL2scH,

TssL2scL

 to SCK  or SCK  Input

TCY

—ns

TscH

SCK Input High Time

(Slave mode)

Continuous

1.25 TCY + 30

—

71A

Single Byte

—

(Note 1)

TscL

SCK Input Low Time

(Slave mode)

Continuous

1.25 TCY + 30

—

72A

Single Byte

—

(Note 1)

TdiV2scH,

TdiV2scL

Setup Time of SDI Data Input to SCK Edge

100

—

73A

Tb2b

Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40

—

(Note 2)

TscH2diL,

TscL2diL

Hold Time of SDI Data Input to SCK Edge

100

—

TdoR

SDO Data Output Rise Time

—

TdoF

SDO Data Output Fall Time

—

TssH2doZ SS

 to SDO Output High-Impedance

TscR

SCK Output Rise Time (Master mode)

—

TscF

SCK Output Fall Time (Master mode)

—

TscH2doV

TscL2doV

SDO Data Output Valid after SCK Edge

—

TscH2ssH

TscL2ssH

 after SCK edge

1.5 TCY + 40

—

Note 1:

Requires the use of Parameter #73A.

Only if Parameter #71A and #72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

75, 76

SDI

MSb

LSb

bit 6 - - - - - -1

MSb In

bit 6 - - - -1

LSb In

Note:

Refer to Figure 26-4 for load conditions.

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