PIC18F23K20-ESLASHML datasheet(402/456 Pages) MICROCHIP

402 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 402

 2010 Microchip Technology Inc.

FIGURE 26-22:

A/D CONVERSION TIMING

TABLE 26-25: A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

Note

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEP instruction to be executed.

This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

.. .

. . .

TCY

Param

No.

Symbol

Characteristic

Min

Max

Units

Conditions

130

TAD

A/D Clock Period

0.7

25.0(1)

sTOSC based,

-40

C to +85C

0.7

4.0(1)

sTOSC based,

+85

C to +125C

1.0

4.0

s

FRC mode, VDD

2.0V

131

TCNV

Conversion Time

(not including acquisition time) (Note 2)

TAD

132

TACQ

Acquisition Time (Note 3)

1.4

—

sVDD = 3V, Rs = 50

135

TSWC

Switching Time from Convert

 Sample

—

(Note 4)

136

TDIS

Discharge Time

TAD

Legend: TBD = To Be Determined

Note 1:

The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

ADRES register may be read on the following TCY cycle.

The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50

.

On the following cycle of the device clock.

PIC18F23K20-E/ML Datasheet(PDF) 402 Page - Microchip Technology

PIC18F23K20-E/ML Datasheet(HTML) 402 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL