PIC18F23K20-ESLASHML datasheet(190/456 Pages) MICROCHIP

190 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 190

 2010 Microchip Technology Inc.

16.4.8

OPERATION IN POWER-MANAGED

MODES

In Sleep mode, all clock sources are disabled. Timer2

will not increment and the state of the module will not

change. If the ECCP pin is driving a value, it will con-

tinue to drive that value. When the device wakes up, it

will continue from this state. If Two-Speed Start-ups are

enabled, the initial start-up frequency from HFINTOSC

and the postscaler may not be stable immediately.

In PRI_IDLE mode, the primary clock will continue to

clock the ECCP module without change. In all other

power-managed modes, the selected power-managed

mode clock will clock Timer2. Other power-managed

mode clocks will most likely be different than the

primary clock frequency.

16.4.8.1

Operation with Fail-Safe

Clock Monitor

If the Fail-Safe Clock Monitor is enabled, a clock failure

will force the device into the RC_RUN Power-Managed

mode and the OSCFIF bit of the PIR2 register will be

set. The ECCP will then be clocked from the internal

oscillator clock source, which may have a different

clock frequency than the primary clock.

See the previous section for additional details.

16.4.9

EFFECTS OF A RESET

Both Power-on Reset and subsequent Resets will force

all ports to Input mode and the CCP registers to their

Reset states.

This forces the enhanced CCP module to reset to a

state compatible with the standard CCP module.

PIC18F23K20-E/ML Datasheet(PDF) 190 Page - Microchip Technology