PIC18F23K20-ESLASHML datasheet(194/456 Pages) MICROCHIP

194 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 194

 2010 Microchip Technology Inc.

17.3.1

REGISTERS

The MSSP module has four registers for SPI mode

operation. These are:

• SSPCON1 – Control Register

• SSPSTAT – STATUS register

• SSPBUF – Serial Receive/Transmit Buffer

• SSPSR – Shift Register (Not directly accessible)

SSPCON1 and SSPSTAT are the control and STA-

TUS registers in SPI mode operation. The SSPCON1

the SSPSTAT are read-only. The upper two bits of the

SSPSTAT are read/write.

SSPSR is the shift register used for shifting data in

and out. SSPBUF provides indirect access to the

SSPSR register. SSPBUF is the buffer register to

which data bytes are written, and from which data

bytes are read.

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

During

transmission,

the

SSPBUF

not

double-buffered. A write to SSPBUF will write to both

SSPBUF and SSPSR.

SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0

R-0

SMP

CKE

D/A

R/W

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

SMP: Sample bit

SPI Master mode:

= Input data sampled at end of data output time

= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode.

bit 6

CKE: SPI Clock Select bit(1)

= Output data changes on clock transition from active to idle

= Output data changes on clock transition from idle to active

bit 5

D/A: Data/Address bit

Used in I2C mode only.

bit 4

P: Stop bit

Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.

bit 3

S: Start bit

Used in I2C mode only.

bit 2

R/W: Read/Write Information bit

Used in I2C mode only.

bit 1

UA: Update Address bit

Used in I2C mode only.

bit 0

BF: Buffer Full Status bit (Receive mode only)

= Receive complete, SSPBUF is full

= Receive not complete, SSPBUF is empty

Note 1:

Polarity of clock state is set by the CKP bit of the SSPCON1 register.

PIC18F23K20-E/ML Datasheet(PDF) 194 Page - Microchip Technology

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