PIC24F16KA102 datasheet(156/254 Pages) MICROCHIP

156 / 254 page

PIC24F16KA102 FAMILY

DS39927B-page 154

Preliminary

bit 7-0

CAL<7:0>:

RTC Drift Calibration bits

01111111

= Maximum positive adjustment; adds 508 RTC clock pulses every one minute

01111111

= Minimum positive adjustment; adds 4 RTC clock pulses every one minute

00000000

= No adjustment

11111111

= Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute

10000000

= Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute

Note 1:

The RCFGCAL register is only affected by a POR.

A write to the RTCEN bit is only allowed when RTCWREN = 1.

This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.

PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0

—

bit 15

bit 8

U-0

R/W-0

U-0

—

SMBUSDEL

OC1TRIS

RTSECSEL1(1) RTSECSEL0(1)

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-5

Unimplemented:

Read as ‘0’

bit 4-3

Described in Section 15.0 “Output Compare” and Section 17.0 “Inter-Integrated Circuit (I2C™)”.

bit 2-1

RTSECSEL<1:0>:

RTCC Seconds Clock Output Select bits(1)

= Reserved; do not use

= RTCC source clock is selected for the RTCC pin (can be LPRC or SOSC, depending on the

RTCCKSEL (FDS<5>) bit setting)

= RTCC seconds clock is selected for the RTCC pin

= RTCC alarm pulse is selected for the RTCC pin

bit 0

Unimplemented:

Read as ‘0’

Note 1:

To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.

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